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DATA STRUCTURE-I (IT111 & CS113)

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IIST - 2nd year - Analog & Digital Communication

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Practicals: Study of Amplitude Modulation and Demodulation. Study of Frequency Modulation and Demodulation. Study of Time Division Multiplexing.  To study different types of signal samplings . Study of Amplitude Shift Keying (ASK) System.  Study of Phase shift key system (PSK) . Study of Frequency shift key system (FSK) . Study of Pulse Code Modulation. (no longer in course ) Study of Pulse Amplitude Modulation and Demodulation.  Study of Pulse Width Modulation and Demodulation.  Study of Pulse Position modulation
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IIST - 2nd Year - Digital Circuit and Design

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Syllabus UNIT 1: Number systems & codes Number systems & codes, Binary arithmetic, Boolean algebra and switching function. Minimization of switching function, Concept of prime implicant, Karnaugh map method, Quine McCluskey’s method,Cases with don’t care terms, Multiple output switching function. UNIT 2: Introduction to logic gates Introduction to logic gates, Universal gate, Half adder,Half subtractor, Full adder, Full subtractor circuits, Series & parallel addition, BCD adders, Look-ahead carry generator. UNIT 3: Linear wave shaping circuits Linear wave shaping circuits, Bistable, Monostable & Astable multivibrator, Schmitt Trigger circuits & Schmitt-Nand gates. Logic families:RTL, DTL, All types of TTL circuits, ECL, I2L, PMOS, NMOS, & CMOS logic, Gated flip- flops and gated multivibrator, Interfacing between TTL to MOS. UNIT 4: Encoders, Decoders Decoders, Encoders, Multiplexers, Demultiplexers, Introduction to various semiconductor memories, ...
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IIST - 2nd Year - Digital Circuit and Design

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Practicals: To study and test of operation of all logic gates for various IC's. Verification of Demorgan's theorm. To construct of half adder and full adder. To construct of half subtractor and full subtractor. Verification of versatility of NAND gate. Verification of versatility of NOR gate. Designing and verification of property of full adder. Design A BCD to excess-3 code conveter. Design a Multiplexer/Demultiplexer. Design of counters.
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